1. Field of the Invention
The present invention relates to an integrated circuit device, and more particularly, to a clock generating circuit for generating a clock signal synchronizing with a reference signal.
2. Description of the Related Art
Usually, a synchronous dynamic random access memory (SDRAM) includes a clock generating circuit for generating an internal clock signal synchronizing with an external clock signal. Since many operations of an SDRAM including data input/output are with reference to the internal clock signal, the clock signal generating circuit which generates the internal clock signal is an important circuit to SDRAM.
Conventionally, a phase-locked loop (PLL) or a delay-locked loop (DLL) is used in SDRAMs to synchronize an internal clock signal with an external clock signal. PLL or DLL uses a feedback circuit within SDRAM and generates an internal clock signal which derives from and synchronizes with an external clock signal.
Recently, SDRAM employs a mode for minimizing the power consumption by reducing the supply of power when an input/output operation is not performed. A state in which the supply of power is reduced is referred to as a power down mode or a sleep mode, and a mode in which an input/output operation is performed is referred to as an activated mode.
Typically, the operation of an SDRAM commence after the PLL or DLL reaches stabilization, when changing from a power down mode to an activated mode. An internal clock signal generated by the stabilized PLL or DLL is used to clock and synchronize internal circuits. Since PLL or DLL includes a feedback circuit, it usually takes from several hundreds of cycles through several thousands of cycles to stabilize the PLL or DLL. The time required for stabilizing PLL or DLL greatly affects the operating speed of an entire system.
Hence, circuit designers have sought effective clock synchronization methods which change from a power down mode to an activated mode rapidly and consume a small amount of power, especially in power down mode. One of these methods is a synchronous mirror delay method, which duplicates internal electrostatic capacity of an SDRAM and delay time with respect to the characteristics of an input/output multiplexer within SDRAM by using an internal mirror delay circuit. With the copied capacity and delay time, the synchronous mirror delay method controls the input/output signal of SDRAM.
A synchronous mirror delay method is disclosed by Saeki et al. in xe2x80x9cA 2.5 ns Clock Access 250 MHz 256 Mb SDRAM With a Synchronous Mirror Delayxe2x80x9d, IEEE J. Solid State Circuits, vol. 31, pp. 1656-1664, November 1996. According to this synchronous mirror delay method, the time required for the DLL of a clock generator to be stabilized is reduced to two cycles.
The synchronous mirror delay method disclosed by Saeki et al. is implemented by a digital circuit, which digitizes and duplicates the internal electrostatic capacity of SDRAM and a delay time based on characteristics of an input/output multiplexer within an SDRAM. However, during a digitizing process, quantization errors may occur.
A method to solve the above described problem is disclosed in the commonly assigned Korean Patent Application No. 98-34882, entitled xe2x80x9cInternal Clock Generating Circuit with Analog Pumping Structure.xe2x80x9d The disclosure in its entirety of Korean Patent Application No. 34882 is incorporated by reference herein. The invention disclosed in Korean Patent Application No. 34882 eliminates the delay error of an output clock due to a quantization error.
However, even the mirror delay circuit disclosed in the Korea Patent Application No. 34882 may not accurately mirror a desired delay time when there are changes in fabrication conditions such as temperature and pressure. The difference between the delay time of a mirror delay circuit and the delay time of an actual circuit may cause synchronization error of an internal clock signal against an external clock signal, and may further decrease the operating speed of the SDRAM.
To solve the above problems, it is an objective of the present invention to provide a clock generating circuit which generates an internal clock signal synchronizing with an external clock signal within a short time, wherein the clock generating circuit rapidly eliminates the error between the internal clock signal and the external clock signal which may occur between the delay time of a mirror delay circuit and the delay time of an actual circuit.
Accordingly, to achieve the above objective, there is provided a clock generating circuit for generating an internal clock signal synchronizing with an external clock signal. The clock generating circuit includes a controller for receiving the internal clock signal and the reference clock signal and generating first and second divided signals, wherein the first and the second divided signals have different phases and a 1/(2N) (N is a natural number) frequency of the reference clock signal; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; and a fast comparator for providing a pre-clock signal for generating the internal clock signal, in response to the first and the second pumping signals, wherein the pre-clock signal responds to a voltage level based on at least one of the first and the second pumping signals with respect to a predetermined reference voltage.
In another embodiment, there is provided a clock generating circuit for generating an internal clock signal synchronizing with a reference clock signal. The clock generating circuit includes a controller for receiving the internal clock signal and the reference clock signal and generating first and second divided signals, wherein the first and the second divided signals have different phases and a 1/(2N) (N is a natural number) frequency of the reference clock signal; a linear current pump for generating first and second pumping signals in response to the first and the second divided signals, wherein each of the first and the second pumping signals has a level-up time rate and a level-down time rate which are the same; a fast comparator for providing a pre-clock signal in response to the first and the second pumping signals, wherein the pre-clock signal responds to a voltage level based on at least one of the first and the second pumping signals with respect to a reference voltage; a selection delay unit for delaying the pre-clock signal by a predetermined variable delay time to generate the internal clock signal; and a delay regulator for providing a duty control signal for controlling the duty ratio of the internal clock signal to the selection delay unit.